1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device including via holes passing through a semiconductor substrate and to a semiconductor device.
2. Description of the Related Art
Electronic components have recently been increased in integration density and mounting density accompanying the demand for improving the functions of electronic apparatuses and compacting them. Therefore, MCM (multi-chip module) or SIP (system-in package) type semiconductor devices using flip-chip mounting are becoming mainstream. Such semiconductor devices include a semiconductor device having a chip-on-chip (COC) structure in which a second semiconductor chip is flip-chip connected on a first semiconductor chip.
FIG. 16 is a sectional view showing the schematic constitution of a general semiconductor device having a chip-on-chip structure. The semiconductor device shown in FIG. 16 includes a first semiconductor chip 1 and a second semiconductor chip 2. The second semiconductor chip 2 is flip-chip mounted at a substantially central portion of a main surface of the first semiconductor chip 1 using a plurality of bumps 3. Also, a plurality of electrode pads 4 is formed in the peripheral region of the first semiconductor chip 1 so as to surround a region in which the semiconductor chip 2 is mounted. Further, a dam 5 is provided between the chip mounting region and the region in which the electrode pads 4 are formed on the main surface of the first semiconductor chip 1. The dam 5 is formed in a frame shape having a rectangular planar form so as to surround the chip mounting region. Further, the space between the first semiconductor chip 1 and the second semiconductor chip 2 is filled with an under fill material 6 inside the dam 5.
The semiconductor device having the above-described constitution is bonded onto a mounting substrate 7 through an adhesive layer 8 as shown in FIG. 16, and then the electrode pads 4 on the first semiconductor chip 1 are electrically connected to lands 9 on the mounting substrate 7 through bonding wires 10.
For semiconductor devices with a chip-on-chip structure, there has recently been demand for increasing the signal processing speed and decreasing the mounting area. Namely, a semiconductor device to be mounted in a wire bonding system shown in FIG. 16 has problems of signal transmission delay due to the wire length of the bonding wires 10 and securement of a mounting area necessary for drawing the bonding wires 10.
Therefore, as schematically shown in FIG. 17, via holes (through electrodes) 11 are formed in the first semiconductor chip 1 in order to connect layers of the bumps 3 bonded to the upper second semiconductor chip 2 and bumps 12 bonded to the lower mounting substrate 7. This is very advantageous because an increase in the signal transmission speed and a decrease in the mounting area can be realized at the same time.
On the other hand, when via holes are formed, in order to realize a shorter processing time and a narrower pitch, it is necessary to thin a wafer (semiconductor substrate). In order to thin a wafer, back grinding is generally performed. In a method known as a first method for forming via holes, through electrodes are buried in a surface of the wafer, and then the bottoms of the through electrodes are exposed to the outside by grinding the back side of the wafer to form terminal surfaces (refer to Japanese Patent No. 2004-241479).
In a method proposed as a second method for forming via holes, contact holes are formed from the back side of a wafer having an element forming layer including a semiconductor element and wiring formed on the front side thereof so that the contact holes communicate with the wiring layer, and then the contact holes are made conductive to form via holes (refer to Japanese Unexamined Patent Application Publication No. 2006-41450).
In another method known as a third method for forming via holes, through holes are formed from the front side of a semiconductor substrate on which an element forming layer is formed so as to pass through the wafer, and then the through holes are made conductive to form via holes (refer to Japanese Unexamined Patent Application Publication No. 2002-50736).